1. Field of the Invention
The present invention relates to a solid-state imaging device. In particular, the present invention relates to a CMOS type amplification-type solid-state imaging device having a substrate structure and a well structure collecting carries into a photoelectric converter. For example, the present invention is used for digital cameras, mobile phones and mobile apparatuses.
2. Description of the Related Art
The advantage of a CMOS amplification-type solid-state imaging device (hereinafter, referred to as a CMOS image sensor) is a single power supply which operates at a low voltage of, for example, about 3V and consumes low power, for example, about 50 mW of electric power. In the device, a plurality of pixels each included of a photoelectric conversion element and a plurality of transistors have been formed on a semiconductor substrate, thereby achieving a multi-pixel configuration. Each pixel has an amplifying function whereby the potential in a signal charge accumulating part is modulated by the signal charge generated by the photoelectric conversion element and the amplifying transistor in the pixel is modulated according to the modulated potential.
In a conventional CMOS image sensor, a p/p+ substrate is used as a semiconductor substrate. The p/p+ substrate is formed in such a manner that a P epitaxial layer having low impurity concentration is stacked on the surface of a P+ substrate having high impurity concentration with about 5 to 10 μm. The reason for using the p/p+ substrate is as follows. The lifetime of carrier (electron) in the portion (P+ substrate) having high impurity concentration is short in a deep position of the substrate. Specifically, strong light is radiated to the photoelectric conversion element, that is, photo diode, and then, carries are generated. Even if the carrier diffuses up to the depth of the substrate, electrons are re-combined in an area where the lifetime of the carrier is short. Therefore, it is possible to prevent carries generated from the following factors from coming into neighboring photo diodes. The carries overflows from the photo diode because strong light are radiated to the photo diode, or generated by being photo-electrically converted in a deep position of the substrate. Moreover, it is possible to prevent a generation of blooming.
Recently, with scale reduction of devices, if the area of the photo diode is reduced, there is a problem that sensitivity is reduced. The features of the CMOS image sensor is low voltage drive. Thus, it is difficult to widen a depletion layer of the photo diode. For this reason, the sensitivity is improved by widening the depletion layer of the photo diode, and thereby, it is difficult to prevent reduction of the sensitivity resulting from the scale reduction of devices. In order to improve the sensitivity of the CMOS image sensor, it is important that the following substrate structure is employed. According to the substrate structure, carriers are effectively collected into the photo diode. Thus, a p/p+ substrate is used. Namely, the p/p+ substrate has the following two areas. One is an area having low B (boron) concentration at a shallow position of the substrate on the surface thereof. Another is an area having high B concentration at a deep position of the substrate. Thus, the p/p+ substrate has an interface such that the concentration of B rapidly changes. This gives the following advantage. Specifically, even if electrons generated by photoelectric conversion are diffused to a deep position of the substrate, these electrons are bounced back to the surface of the substrate at the interface where B concentration rapidly changes. Part of the bounced electrons is collected to the photo diode to which light is radiated by diffusion. As a result, the sensitivity is improved.
The CMOS image sensor has another feature. According to the feature, a manufacturing process is close to a logic LSI; therefore, a signal processing circuit is manufactured in the same manufacturing line as an imaging element. Thus, the imaging element and the signal processing circuit are formed on one chip. As described above, the CMOS image sensor is driven using a single power and at low voltage.
One-chip CMOS image sensor thus formed can use a P substrate or p/p+ substrate in accordance with the logic LSI manufacturing process. If the p/p+ substrate is used, the back side of a wafer is grounded, and a stable and favorite waveform is obtained as a pulse signal generated by a logic circuit and an analog circuit. Therefore, multi-pixel or high speed operation is possible.
The advanced CMOS image sensor has multi-pixel. When scale reduction of pixel is made without changing the size of a sensor chip, the light receiving area of the photo diode is reduced, and thereby, a reduction of sensitivity of the photo diode becomes problem. Thus, it is desired to improve the sensitivity. The CMOS image sensor is driven at low voltage; therefore, if the photo diode is formed in a P type area, it is difficult to widen the depletion layer of the photo diode. For this reason, electrons photo-electrically converted between photo diodes leak to neighboring pixels. As a result, sensitivity reduction and color mixture deterioration are caused.
Accordingly, the depletion layer of the photo diode is widened to improve sensitivity, and thereby, it is difficult to employ a method of preventing the sensitivity from being reduced resulting from scale reduction. Based on the foregoing background, it is desired to provide the technique of improving the sensitivity of the CMOS image sensor having multi-pixel. The foregoing technique is disclosed in Jpn. Pat. Appln. KOKAI Publications No. 2001-160620 and 2001-223351. Moreover, it is desired to develop the technique of preventing blooming and image quality deterioration of color mixture.
There is provided a solid-state imaging device using an n/p+ substrate as a substrate structure overcoming the foregoing both technical problems. The solid-state imaging device is described in the specification of assigner, that is, U.S. patent application Ser. No. 11/776,791. The n/p+ substrate has a structure such that an n type semiconductor layer is deposited on a p+ substrate (base substrate) by an epitaxial growth process. P (phosphorus) ion is injected into the n type semiconductor layer using an ion accelerator to form an N type semiconductor layer for the photo diode. By doing so, the depletion layer of the photo diode is easy to widen as compared with the p/p+ substrate. In this way, carries are effectively collected to the photo diode without stepping up a drive voltage of the CMOS image sensor. Therefore, it is expected to provide high sensitivity and an increase of saturating signal. In addition, it is possible to use the shortness of the lifetime of carrier; therefore, blooming and image quality deterioration of color mixture are prevented. Thus, a CMOS image sensor is manufactured using the foregoing n/p+ substrate, and thereby, the foregoing problem can be solved.
On the other hand, in the CMOS image sensor using the n/p+ substrate, when strong light is incident, a signal overflows from the photo diode and flows into peripheral pixels, that is, blooming occurs. As described above, in the p+ substrate, the lifetime of carrier (electron) is short. For example, strong light and long wavelength light are incident on the photo diode, and even if carries are generated in the substrate, and thereafter, diffuse up to the deep position of the substrate, electrons are re-combined in an area where the lifetime of these carriers is short. As a result, carries generated in the deep position of the substrate do not leak into neighboring photo diodes, and blooming is prevented. However, a large number of carriers generated in a shallow area of the substrate leaks to peripheral pixels without being re-combined, and this is a factor of causing blooming.